1. Technical Field
The present invention relates in general to data processing systems and in particular to kernel process management. Still more particularly, the present invention relates to an improved method, system and program product for associating threads from non-related processes.
2. Description of the Related Art
The memory system of a typical personal computer includes one or more nonvolatile mass storage devices, such as magnetic or optical disks, and a volatile random access memory (RAM), which can include both high speed cache memory and slower main memory. In order to provide enough addresses for memory-mapped input/output (I/O) as well as the data and instructions utilized by operating system and application software, the processor of a personal computer typically utilizes a virtual address space that includes a much larger number of addresses than physically exist in RAM. Therefore, to perform memory-mapped I/O or to access RAM, the processor maps the virtual addresses into physical addresses assigned to particular I/O devices or physical locations within RAM.
In the PowerPC™ RISC architecture, the virtual address space is partitioned into a number of memory pages, which each have an address descriptor called a Page Table Entry (PTE). The PTE corresponding to a particular memory page contains the virtual address of the memory page as well as the associated physical address of the page frame, thereby enabling the processor to translate any virtual address within the memory page into a physical address in memory. The PTEs, which are created in memory by the operating system, reside in Page Table Entry Groups (PTEGs), which can each contain, for example, up to eight PTEs. According to the PowerPC™ architecture, a particular PTE can reside in any location in either of a primary PTEG or a secondary PTEG, which are selected by performing primary and secondary hashing functions, respectively, on the virtual address of the memory page. In order to improve performance, the processor also includes a Translation Lookaside Buffer (TLB) that stores the most recently accessed PTEs for quick access.
In conventional computer operating systems (OSs), multiple processes' threads can share a single physical processor. Each process thread periodically is executed by the processor for a pre-defined amount of time (often called a time slice). However, an active process thread rarely utilizes all of the multiple execution units within a modern processor during a clock cycle. Simultaneous multithreading (SMT) enables multiple processes' threads to execute different instructions in the same clock cycle, thereby using execution units that would otherwise be left idle by a single process thread.
Application programs often require assistance from another application (also referred to as a “partner application”) or kernel process, such as a device driver or daemon, to complete one or more operations. In some cases, the partner application or assisting kernel process is unknown at the time the application program is coded since application programs, data processing system hardware and operating systems are frequently independently developed or developed by different vendors. Application programs that rely upon assistance of partner applications or assisting kernel processes often exhibit sub-optimal performance when memory constraints or other operating conditions cause the application programs to be paged into memory, since the partner application/process will also be paged into memory in a “lagging” manner. Paging a partner application/process into memory in a lagging manner delays the execution of an assisted application that is awaiting the page in of the partner application in the execution path.